Experimental Support for Reconfigurable Application-Specific Accelerators

New computer architectures are being proposed and will be implanted in the next few years. A common trend to improve the system performance is to include some reconfigurable logic components into future multi-core chips. Several prototypes already exist but there still is a lack of support from the programming models, the compilers and the operating system. Reconfigurable architectures enable a new execution model based on hardware accelerators. There have been several efforts in the last few years to extend the thread abstraction to include the characteristics of these new reconfigurable elements. However, since the thread abstraction was conceived to abstract the CPU, the inherent model is different from what hardware accelerators should expect. In this paper we present a new way of managing hardware accelerators. We propose a new programming and execution model for hardware accelerators based on the processing unit abstraction. We study the relationship between hardware accelerators and the processor architecture, exploring the features that the new reconfigurable architectures should provide to the operating system. We also show how a prototype hardware accelerator achieves a 1.78x speed-up over the software implementation of the same functionality, out of a 41x potential speed-up, due to the data communication overhead. Finally we show our work on dynamic partial reconfiguration and how it enables using the processing unit abstraction to provide virtual reconfigurable logic.